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Freescale Semiconductor Product Brief
Document Number: MC56F8025PB Rev. 0, 09/2006
56F8025 Digital Signal Controller Product Brief
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56F8025 Description
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Contents
56F8025 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Signal Controller Core . . . . . . . . . . . . . . . . . . . . . Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Circuits for 56F8025. . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . 56F8025 Package and Pin-Out . . . . . . . . . . . . . . . . . . . . 1 3 3 3 5 6 7
The 56F8025 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8025 is well-suited for many applications. The 56F8025 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general-purpose inverters, smart sensors, fire and security systems, switched-mode power supply, power management, and medical monitoring applications. The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications.
(c) Freescale Semiconductor, Inc., 2006. All rights reserved. * Preliminary--Subject to Change Without Notice
56F8025 Description
The 56F8025 supports program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8025 also offers up to 35 General-Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F8025 Digital Signal Controller includes 32KB of Program Flash and 4KB of Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages. Program Flash page erase size is 512 Bytes (256 Words). A full set of programmable peripherals -- PWM, ADCs, QSCI, QSPI, I2C, PIT, Quad Timers, DACs, and analog comparators -- supports various applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).
RESET or GPIOA 4
VCAP 2
VDD 2
VSS_IO 3
VDDA
VSSA
11
PWM or TMRA or CMP or GPIOA
Program Controller and Hardware Looping Unit
JTAG/EOnCE Port or GPIOD
Digital Reg
Analog Reg
16-Bit 56800E Core
Low-Voltage Supervisor Bit Manipulation Unit
Address Generation Unit
Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators
DAC
4
PAB PDB CDBR CDBW
AD0 ADC or CMP or GPIOC
Memory
Program Memory 16K x 16 Flash Unified Data / Program RAM 2K x 16
XDB2 XAB1 XAB2 PAB PDB CDBR CDBW
R/W Control
4
AD1
System Bus Control
Programmable Interval Timer
IPBus Bridge (IPBB)
I2C or CMP or GPIOB
QSPI or PWM or I2C or TMRA or GPIOB 4
QSCI or PWM or I2C or TMRA or GPIOB
COP/ Watchdog
Interrupt Controller
System Integration Module
P O R
O Clock S Generator* C
XTAL, CLKIN, or GPIOD EXTAL or GPIOD
2
3
*Includes On-Chip Relaxation Oscillator
Figure 1. 56F8025 Block Diagram
56F8025 Digital Signal Controller Product Brief, Rev. 0 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Digital Signal Controller Core
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Digital Signal Controller Core
Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators, including extension bits 32-bit arithmetic and logic multi-bit shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions Controller-style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent real-time debugging
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* * *
Memory
Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security and protection that prevent unauthorized users from gaining access to the internal Flash On-chip memory -- 32KB of Program Flash -- 4KB of Unified Data/Program RAM EEPROM emulation capability using Flash
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Peripheral Circuits for 56F8025
One multi-function six-output Pulse Width Modulator (PWM) module -- Up to 96MHz PWM operating clock -- 15 bits of resolution -- Center-aligned and edge-aligned PWM signal mode -- Four programmable fault inputs with programmable digital filter -- Double-buffered PWM registers -- Each complementary PWM signal pair allows selection of a PWM supply source from: - - - - - PWM generator External GPIO Internal timers Analog comparator outputs ADC conversion result which compares with values of ADC high- and low-limit registers to set PWM output
56F8025 Digital Signal Controller Product Brief, Rev. 0
Freescale Semiconductor
Preliminary--Subject to Change Without Notice
3
Peripheral Circuits for 56F8025
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Two independent 12-bit Analog-to-Digital Converters (ADCs) -- 2 x 4 channel inputs -- Supports both simultaneous and sequential conversions -- ADC conversions can be synchronized by both PWM and timer modules -- Sampling rate up to 2.67MSPS -- 16-word result buffer registers Two internal 12-bit Digital-to-Analog Converters (DACs) -- 2 microsecond settling time when output swing from rail to rail -- Automatic waveform generation generates square, triangle and sawtooth waveforms with programmable period, update rate, and range One 16-bit multi-purpose Quad Timer module (TMR) -- Up to 96MHz operating clock -- Eight independent 16-bit counter/timers with cascading capability -- Each timer has capture and compare capability -- Up to 12 operating modes One Queued Serial Communication Interface (QSCI) with LIN Slave functionality -- Full-duplex or single-wire operation -- Two receiver wake-up methods: - Idle line - Address mark -- Four-bytes-deep FIFOs are available on both transmitter and receiver One Queued Serial Peripheral Interfaces (QSPI) -- Full-duplex operation -- Master and slave modes -- Four-words-deep FIFOs available on both transmitter and receiver -- Programmable Length Transactions (2 to 16 bits) One Inter-Integrated Circuit (I2C) port -- Operates up to 400kbps -- Supports both master and slave operation -- Supports both 10-bit address mode and broadcasting mode Three 16-bit Programmable Interval Timers (PITs) Two analog Comparators (CMPs) -- Selectable input source includes external pins, DACs -- Programmable output polarity -- Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs
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56F8025 Digital Signal Controller Product Brief, Rev. 0 4 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Recommended Operating Conditions
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-- Output falling and rising edge detection able to generate interrupts Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources Up to 35 General-Purpose I/O (GPIO) pins with 5V tolerance Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals Clock sources: -- On-chip relaxation oscillator -- External clock: Crystal oscillator, ceramic resonator, and external clock source JTAG/EOnCE debug programming interface for real-time debugging
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Recommended Operating Conditions
Table 1. Recommended Operating Conditions (VREFL x= 0V, VSSA = 0V, VSS = 0V)
Characteristic Symbol VDD, VDDA VREFHx VDD VSS FSYSCLK 1 0 VIH VIL VIHOSC Pin Groups 1, 2 Pin Groups 1, 2 Pin Group 4 VDDA - 0.8 2.0 VILOSC VIA Pin Group 4 Pin Group 3 -0.3 0.0 VDDA + 0.3 VDDA + 0.3 0.8 VDDA V V V 2.0 -0.3 32 32 5.5 0.8 MHz V V Notes Min 3 3.0 -0.1 -0.3 0 0 Typ 3.3 Max 3.6 VDDA 0.1 0.3 Unit V V V V
Supply voltage ADC Reference Voltage High Voltage difference VDD_IO to VDDA Voltage difference VSS_IO to VSSA Device Clock Frequency Using relaxation oscillator Using external clock source Input Voltage High (digital inputs) Input Voltage Low (digital inputs) Oscillator Input Voltage High XTAL not driven by an external clock XTAL driven by an external clock source Oscillator Input Voltage Low Analog Input Voltage
56F8025 Digital Signal Controller Product Brief, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5
Product Documentation
Table 1. Recommended Operating Conditions (continued) (VREFL x= 0V, VSSA = 0V, VSS = 0V)
Characteristic Output Source Current High at VOH min.)1 When programmed for low drive strength When programmed for high drive strength Output Source Current Low (at VOL max.)1 When programmed for low drive strength When programmed for high drive strength Ambient Operating Temperature (Automotive) Ambient Operating Temperature (Extended Industrial) Flash Endurance (Program Erase Cycles) Flash Data Retention
1
Symbol IOH
Notes Pin Group 1 Pin Group 1
Min -- -- -- -- -40 -40
Typ
Max -4 -8 4 8 125 105 -- --
Unit mA
IOL Pin Groups 1, 2 Pin Groups 1, 2 TA TA NF TR TA = -40C to 125C TJ <= 70C average mA C C cycles years
10,000 15
Total chip source or sink current cannot exceed 75mA
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Product Documentation
The documents listed in Table 2 are required for a complete description and proper design with the 56F8025. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.com
Table 2. 56F8025 Chip Documentation
Topic DSP56800E Reference Manual 56F802X and 56F803X Peripheral Reference Manual 56F802X and 56F803X Serial Bootloader User Guide 56F8025 Technical Data Sheet 56F8025 Errata Description Detailed description of the 56800E family architecture, 16-bit Digital Signal Controller core processor, and the instruction set Detailed description of peripherals of the 56F802x and 56F803x family of devices Detailed description of the Serial Bootloader in the 56F802x and 56F803x family of devices Electrical and timing specifications, pin descriptions, and package descriptions (this document) Details any chip issues that might be present Order Number DSP56800ERM
MC56F80XXRM
56F80XXBLUG
MC56F8025 MC56F8025E
56F8025 Digital Signal Controller Product Brief, Rev. 0 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor
56F8025 Package and Pin-Out
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56F8025 Package and Pin-Out
GPIOB11 / COUTB_A GPIOD5 / XTAL / CLKIN
TDO / GPIOD1
TMS / GPIOD3
TDI / GPIOD0
GPIOA0 / PWM0
GPIOA1 / PWM1
GPIOD4 / EXTAL
VDD_IO
VSS_IO
GPIOB6 / RXD0 / SDA / CLKIN GPIOB1 / SS0 / SDA GPIOB7 / TXD0 / SCL GPIOB5 / TA1 / FAULT3 / CLKIN GPIOA9 / FAULT2 / TA3 / CINB1 GPIOA11 / CINB2 GPIOC4 / ANB0 & CINB3 GPIOC5 / ANB1 GPIOC6 / ANB2 / VREFHB GPIOC7 / ANB3 / VREFLB VDDA
ORIENTATION MARK
VCAP
GPIOA3 / PWM3
PIN 34 PIN 1
GPIOA2 / PWM2 GPIOA4 / PWM4 / TA2 / FAULT1 GPIOB0 / SCLK0 / SCL VDD_IO VSS_IO GPIOA5 / PWM5 / TA3 / FAULTA2 GPIOA8 / FAULTA1 / TA2 / CINA1
PIN 12
PIN 23
GPIOA10 / CINA2 GPIOA6 / FAULT0 / TA0 GPIOB2 / MISO0 / TA2 / PSRC0
GPIOC0 / ANA0 & CINA3
GPIOC1 / ANA1
Figure 2. Top View, 56F8025 48-Pin LQFP Package
Peripheral pins in bold identify the reset state in Table 3.
56F8025 Digital Signal Controller Product Brief, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7
GPIOB3 / MOSI0 / TA3 / PSRC1
TCK / GPIOD2
GPIOC2 / ANA2 / VREFHA
GPIOC3 / ANA3 / VREFLA
GPIOB10 / COUTA_A
RESET / GPIOA7
VSS_IO
VSSA
VCAP
56F8025 Package and Pin-Out
Table 3. 56F8025 44-Pin LQFP Package Identification by Pin Number1
Pin # 1 2 Signal Name GPIOB6 RXD0 / SDA / CLKIN GPIOB1 SS0 / SDA GPIOB7 TXD0 / SCL GPIOB5 TA1 / FAULT3 / CLKIN GPIOA9 FAULT2 / TA3 / CINB1 GPIOA11 CINB2 GPIOC4 ANB0 &CINB3 GPIOC5 ANB1 GPIOC6 ANB2 / VREFHB GPIOC7 ANB3 / VREFLB VDDA Pin # 12 13 Signal Name VSSA GPIOC3 ANA3 / VREFLA GPIOC2 ANA2 / VREFHA GPIOC1 ANA1 GPIOC0 ANA0 & CINA3 VSS_IO VCAP TCI GPIOD2 GPIOB10 COUTA_A RESET GPIOA7 GPIOB3 MOSI0 / TA3 / PSRC1 Pin # 23 24 Signal Name GPIOB2 MISO0 / TA2 / PSRC0 GPIOA6 FAULT0 / TA0 GPIOA10 CINA2 GPIOA8 FAULT1 / TA2 / CINA1 GPIOA5 PWM5 / TA3 / FAULT2 VSS_IO VDD_IO GPIOB0 SCLK0 / SCL GPIOA4 PWM4 / TA2 / FAULT1 GPIOA2 PWM2 GPIOA3 PWM3 Pin # 34 35 Signal Name VCAP VDD_IO VSS_IO GPIOD5 XTAL / CLKIN GPIOD4 EXTAL GPIOA1 PWM1 GPIOA0 PWM0 TDI GPIOD0 GPIOB11 COUTB_A TMS GPIOD3 TDO GPIOD1
3
14
25
36
4 5 6 7 8 9
15 16 17 18 19 20
26 27 28 29 30 31
37 38 39 40 41 42
10
21
32
43
11
22
33
44
1
Alternate signals are in italic
56F8025 Digital Signal Controller Product Brief, Rev. 0 8 Preliminary--Subject to Change Without Notice Freescale Semiconductor
56F8025 Package and Pin-Out
Figure 3. 56F8025 44-Pin LQFP Mechanical Information
Please see www.freescale.com for the most current case outline.
56F8025 Digital Signal Controller Product Brief, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9
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56F8025 Digital Signal Controller Product Brief, Rev. 0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11
How to Reach Us:
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Rev. 0 09/2006
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Preliminary--Subject to Change Without Notice

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